This invention relates to testing, and more particularly, to rapid testing techniques for integrated circuits.
Integrated circuits are generally tested before being sold. Testing can reveal memory faults that arise during device manufacturing. For example, testing may reveal that a particular memory array cell is stuck at a logical one value or that it is impossible to read data from a particular memory array cell. Testing may also reveal faults in other logic circuits. Identifying errors such as these allows integrated circuits to be repaired or discarded as appropriate.
To thoroughly exercise a circuit under test, it is often desirable to perform circuit tests over a range of clock speeds. For example, it may be desirable to test a circuit at ten different clock speeds. By testing the circuit at a variety of clock speeds, more accurate test results may be obtained. For example, it may be possible to precisely identify the maximum clock speed at which certain circuit functions operate. This may help a manufacturer identify which circuits should be discarded or repaired. Circuits may also be categorized by their maximum clock speed, which allows parts to be binned.
Conventional circuit testing arrangements allocate a fixed amount of test time for each clock speed test iteration. Test iterations that are associated with relatively faster clocks tend to take less time to complete than test iterations that are associated with relatively slower clocks. As a result, there can be a nonnegligible amount of overhead time associated with performing a test when a fixed amount of test time is allocated for each test iteration regardless of the clock speed associated with that iteration.
It would therefore be desirable to be able to provide improved arrangements for performing circuit testing at multiple clock speeds.